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Digital DC/DC PMBus 12A Module
ZL9101M
The ZL9101M is a 12A variable output step-down PMBus-compliant digital power supply. Included in the module is a high performance digital PWM controller, power MOSFETs, an inductor, and all the passive components required for a complete DC/DC power solution. The ZL9101M operates over a wide input voltage range and supports an output voltage range of 0.6V to 4V, which can be set by external resistors or via PMBus. This high efficiency power module is capable of delivering 12A. Only bulk input and output capacitors are needed to finish the design. The output voltage can be precisely regulated to as low as 0.6V with 1% output voltage regulation over line, load, and temperature variations. The ZL9101M features internal compensation, internal soft-start, auto-recovery overcurrent protection, an enable option, and pre-biased output start-up capabilities. The ZL9101M is packaged in a thermally enhanced, compact (15mmx15mm) and low profile (3.5mm) over-molded QFN package module suitable for automated assembly by standard surface mount equipment. The ZL9101M is Pb-free and RoHS compliant.
Features
* Complete Digital Switch Mode Power Supply * Fast Transient Response * External Synchronization * Output Voltage Tracking * Current Sharing * Programmable Soft-start Delay and Ramp * Overcurrent/Undercurrent Protection * PMBus Compliant
Applications
* Server, Telecom, and Datacom * Industrial and Medical Equipment * General Purpose Point of Load
Related Literature
* See AN2033, "Zilker Labs PMBus Command Set - DDC Products" * See AN2034, "Configuring Current Sharing on the ZL2004 and ZL2006"
V DRV 4.5V TO 6.5V 10F 16V 4.7F 16V 4.7F 16V
10F 16V
V IN 5V TO 12V
2 x 22F 16V VDRV POWER GOOD OUTPUT ENABLE Ext Sync DDC Bus
2
PG EN
VIN (EPAD) VOUT (EPAD) ZL9101M SW (EPAD) PGND (EPAD) FB+ FB3 x 47F 16V
3
VDD
VR
V25
V OUT
SYNC DDC SCL
SA
Notes: 1. The I2C/SMBus requires pull-up resistors. Please refer to the I2C/SMBus specifications for more details. 2. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices connected). The 10k default value, assuming a maximum of 100pF per device, provides the necessary 1s pull-up rise time. Please refer to the Digital-DC Bus section for more details. 3. Additional capacitance may be required to meet specific transient response targets 4. The VR, V25, VDRV, and VDD capacitors should be placed no further than 0.5 cm from the pin.
FIGURE 1. 12A APPLICATION CIRCUIT NOTE: Figure 1 represents a typical implementation of the ZL9101M. For PMBus operation, it is recommended to tie the enable pin (EN) to SGND.
January 26, 2011 FN7669.1
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
SGND
I C/SMBus
2
1
SDA VTRK VSET
RTN
ZL9101M Pin Configuration
ZL9101M (21 LD QFN) TOP VIEW
SGND SYNC DDC SCL PG VR EN SA
9 PGND V25 VDD 10 11 12
8
7
6
5
4
3
2
1 21 20 19
SDA VSET VTRK FB+
VDRV
13 14 SW VIN 15 PGND 16
18
FB-
VOUT 17
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14(epad) 15(epad) 16(epad) 17(epad) 18 19 20 21
LABEL SDA SCL SA SYNC PG EN DDC VR SGND PGND V25 VDD VDRV SW VIN PGND VOUT FBFB+ VTRK VSET
TYPE I/O I/O I I/O O I I/O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR I I I I Serial data. Serial clock.
DESCRIPTION
Serial address select pin. Used to assign unique SMBus address to each module. Clock synchronization. Used for synchronization to external frequency reference. Power-good output. Enable input (factory setting active high). Pull-up to enable PWM switching and pull-down to disable PWM switching. Digital-DC bus. (open drain) Interoperability between Zilker Labs modules. Internal 5V reference used to power internal drivers. Signal ground. Connect to low impedance ground plane. Power ground. Connect to low impedance ground plane. Internal 2.5V reference used to power internal circuitry. Input supply voltage for controller. Power supply for internal FET drivers. Connect 10F bypass capacitor to this pin. Drive train switch node Power supply input FET voltage. Power ground. Connect to low impedance ground plane. Power supply output voltage. Output voltage from PWM. Output voltage feedback. Connect to load return of ground regulation point. Output voltage feedback. Connect to output regulation point. Tracking sense input. Used to track an external voltage source. Output voltage selection pin. Used to set VOUT set point and VOUT max.
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ZL9101M Ordering Information
PART NUMBER (Notes 1, 2, 3) ZL9101MIRZ NOTES: 1. Add "-T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by EU exemption 5 (Pb in glass of cathode ray tubes, electronic components and fluorescent tubes). These Intersil RoHS compliant products are compatible with both SnPb and Pb-free soldering operations. These Intersil RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ZL9101M. For more information on MSL please see techbrief TB363. PART MARKING ZL9101M TEMP RANGE (C) -40 to +85 PACKAGE (Pb-Free) 21 LD 15x15 QFN PKG. DWG. # L21.15x15
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ZL9101M Table of Contents
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Derating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Soft-start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Adaptive Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 I2C/SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 I2C/SMBus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Phase Adding/Dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Monitoring via I2C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Non-Volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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ZL9101M
Absolute Maximum Ratings (Note 4)
DC Supply Voltage for VDD Pin . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15.7V Input Voltage for VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15.7V MOSFET Drive Reference for VR Pin . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V 2.5V Logic Reference for V25 Pin. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V MOSFET Driver Power for VDRV Pin . . . . . . . . . . . . . . . . . . . . . .-0.3V to 7.5V Logic I/O Voltage for DDC, EN, FB+, FB-, PG, SA, SCL, SDA,SYNC, VSET Pins . . . . . . . . . . . . . . . -0.3V to 6V ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2000V Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . 1000V Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) QFN Package (Notes 7, 8) . . . . . . . . . . . . . . 11.5 2.2 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55C to +150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Supply Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 5V to 13.2V Input Supply For Controller, VDD (Note 5) . . . . . . . . . . . . . . . . . 5V to 13.2V Driver Supply Voltage, VDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 6.5V Output Voltage Range, VOUT (Note 6). . . . . . . . . . . . . . . . . . . . . 0.54V to 4V Output Current Range, IOUT(DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 15A Operating Junction Temperature Range, TJ . . . . . . . . . . . . . . . . . . . -40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. Voltage measured with respect to SGND 5. VIN supplies the power FETs. VDD supplies the controller. VIN can be tied to VDD. For VDD 5.5V, VDD should be tied to VR. 6. Includes 10% margin limits. 7. JA is simulated in free air with device mounted on a four-layer FR-4 test board (76.2 x 114.3 x 1.6mm) with 80%-coverage, 2-ounce Cu on top and bottom layers, plus two, buried, one-ounce Cu layers with coverage across the entire test board area. Multiple vias were used, with via diameter = 0.3mm on 1.2mm pitch. 8. For JC, the "case" temperature is measured at the center of the package underside.
Electrical Specifications VDD = 12 V, TA = -40C to +85C unless otherwise noted. Typical values are at TA = 25C. Boldface limits apply over the operating temperature range, -40C to +85C.
PARAMETER CONDITIONS MIN (Note 9) TYP (Note 10) MAX (Note 9) UNIT
INPUT AND SUPPLY CHARACTERISTICS
Input Bias Supply Current, IDD Input Bias Shutdown Current, IDDS Input Supply Current, IVIN Driver Supply Current, IVDRV VR Reference Output Voltage (Note 11) V25 Reference Output Voltage (Note 11) fSW = 615kHz, No load EN = 0 V No I2C/SMBus activity VIN = 13.2V, IOUT = 15A, VOUT = 1.2V Not switching VDD > 6V, IVR < 20mA VR > 3V, IV25 < 20mA - - - - 4.5 2.25 20 9.5 1.5 190 5.2 2.5 40 12 2 220 5.7 2.75 mA mA A A V V
OUTPUT CHARACTERISTICS
Line Regulation Accuracy, VOUT/VIN (Note 12) Load Regulation Accuracy, VOUT/IOUT (Note 12) Peak-to-peak Output Ripple Voltage, VOUT (Note 12) Soft-start Delay Duration Range (Notes 11, 13) Soft-start Delay Duration Accuracy (Note 11) VOUT = 1.2V, IOUT = 0A, VIN = 5V to 13.2V IOUT = 0A to 12A, VOUT = 1.2V IOUT = 12A, VOUT = 1.2V, COUT = 3000F Set using I2C/SMBus Turn-on delay (precise mode) (Notes 13, 14) Turn-on delay (normal mode) (Note 15) Turn-off delay (Note 15) Soft-start Ramp Duration Range (Note 11) Set using I2C - - - 2 - - - 0 0.5 0.5 6 - 0.25 -0.25/+4 -0.25/+4 - - - - 200 200 % % mV ms ms ms ms ms
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ZL9101M
Electrical Specifications VDD = 12 V, TA = -40C to +85C unless otherwise noted. Typical values are at TA = 25C. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
PARAMETER Soft-start Ramp Duration Accuracy (Note 11) CONDITIONS MIN (Note 9) - TYP (Note 10) 100 MAX (Note 9) - UNIT s
DYNAMIC CHARACTERISTICS
Voltage Change for Positive Load Step Voltage Change for Negative Load Step IOUT = 6A, slew rate = 2.5A/s, VOUT = 1.2V, COUT = 3000F IOUT = 6A, slew rate = 2.5A/s, VOUT = 1.2V, COUT = 3000F - - 3 3 - - % %
OSCILLATOR AND SWITCHING CHARACTERISTICS (Note 11)
Switching Frequency Range Maximum PWM Duty Cycle Minimum SYNC Pulse Width Input clock Frequency Drift Tolerance External clock source Factory setting 590 95 150 -13 615 - - - 630 - - 13 kHz % ns %
LOGIC INPUT/OUTPUT CHARACTERISTICS (Note 11)
Logic Input Bias Current Logic Input Low, VIL Logic Input High, VIH Logic Output Low, VOL Logic Output High, VOH IOL 4mA (Note 17) IOH -2mA (Note 17) Configurable via I2C/SMBus EN, PG, SCL, SDA pins -10 - 2.0 - 2.25 - - - - - 10 0.8 - 0.4 - A V V V V
FAULT PROTECTION CHARACTERISTICS (Note 11)
UVLO Threshold Range UVLO Set-point Accuracy UVLO Hysteresis Factory setting Configurable via I2C/SMBus UVLO Delay Power Good VOUT Threshold Power Good VOUT Hysteresis Power Good Delay (Note 16) VSEN Undervoltage Threshold Factory setting Factory setting Configurable via I2C/SMBus Factory setting Configurable via I2C/SMBus VSEN Overvoltage Threshold Factory setting Configurable via I2C/SMBus VSEN Undervoltage Hysteresis VSEN Undervoltage/Overvoltage Fault Response Time Factory setting Configurable via I2C/SMBus 2.85 -150 - 0 - - - 0 - 0 - 0 - - 5 - - 3 - - 90 5 - 85 - 115 - 5 16 - 16 150 - 100 2.5 - - 200 - 110 - 115 - - 60 V mV % % s % VOUT % ms % VOUT % VOUT % VOUT % VOUT % VOUT s s
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ZL9101M
Electrical Specifications VDD = 12 V, TA = -40C to +85C unless otherwise noted. Typical values are at TA = 25C. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
PARAMETER Thermal Protection Threshold (Controller Junction Temperature) Thermal Protection Hysteresis NOTES: 9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 10. Parameters with TYP limits are not production tested unless otherwise specified. 11. Parameters are 100% tested for internal controller prior to module assembly. 12. VOUT measured at the termination of the FB+ and FB- sense points. 13. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to approximately 2ms, where in normal mode it may vary up to 4ms. 14. Precise ramp timing mode is only valid when using the EN pin to enable the device rather than PMBus enable. 15. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable signal. 16. Factory setting for Power Good delay is set to the same value as the soft-start ramp time. 17. Nominal capacitance of logic pins is 5pF. Factory setting Configurable via I2C/SMBus CONDITIONS MIN (Note 9) - -40 - TYP (Note 10) 125 - 15 MAX (Note 9) - 125 - UNIT C C C
Typical Performance Curves
100 95 EFFICIENCY (%) 90 85 80 75 70 65 60 0 VIN = 6V fSW = 615kHz 2 4 6 8 10 OUTPUT CURRENT (A) 12 14 16 VOUT = 1.8V VOUT = 1.2V VOUT = 3.3V VOUT = 2.5V EFFICIENCY (%) 100 95 90 85 80 75 70 65 60 0 VIN = 9V fSW = 615kHz 2 4 6 8 10 OUTPUT CURRENT (A) 12 14 16 VOUT = 1.8V VOUT = 1.2V VOUT = 3.3V VOUT = 2.5V
FIGURE 2. EFFICIENCY, VIN = 6V
100 VOUT = 2.5V VOLTAGE DEVIATION (mV) 95 EFFICIENCY (%) 90 85 80 75 70 65 60 0 VIN = 12V fSW = 615kHz 2 4 6 8 10 OUTPUT CURRENT (A) 12 14 16 VOUT = 1.8V VOUT = 1.2V VOUT = 3.3V 35 30 25 20 15 10 5 0 -5 0 0.1
FIGURE 3. EFFICIENCY, VIN = 9V
VIN = 12V VOUT = 1.2V IOUT STEP = 12A to 6A SLEW 2.5A/s
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
FIGURE 4. EFFICIENCY, VIN = 12V
FIGURE 5. DYNAMIC RESPONSE, UNLOADING
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FN7669.1 January 26, 2011
ZL9101M Typical Performance Curves (Continued)
5 VOLTAGE DEVIATION (mV) 0 VOUT (V) -5 -10 -15 VIN = 12V -20 V OUT = 1.2V -25 IOUT STEP = 6A to 12A SLEW 2.5A/s -30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 0 1 2 3 4 5 6 TIME (ms) 7 8 9 10 VIN = 12V VOUT = 1.2V tRISE = 5ms
FIGURE 6. DYNAMIC RESPONSE, LOADING
1.4 1.2 1.0 VOUT (V) 0.8 0.6 0.4 0.2 0 -0.2 0 1 2 3 4 5 6 TIME (ms) 7
FIGURE 7. SOFT-START RAMP-UP
VIN = 12V VOUT = 1.2V tFALL = 5ms
8
9
10
FIGURE 8. RAMP-DOWN
Derating Curves
16 MAX. LOAD CURRENT (A) 14 12 10 8 6 4 2 0 50 60 70 80 90 100 110 AMBIENT TEMPERATURE (C) 120 130 1.0VOUT 3.3VOUT MAX. LOAD CURRENT (A) 16 14 12 10 8 6 4 2 0 50 60 70 80 3.3VOUT 2.5VOUT 1.8VOUT 1.0VOUT 90 100 110 120 130
AMBIENT TEMPERATURE (C)
FIGURE 9A. DERATING CURVE, 5VIN
FIGURE 9B. DERATING CURVE, 12VIN
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FN7669.1 January 26, 2011
ZL9101M Functional Description
Output Voltage Selection
The output voltage may be set to a voltage between 0.6V and 4.0V provided that the input voltage is higher than the desired output voltage by an amount sufficient to prevent the device from exceeding its maximum duty cycle specification. The VSET pin is used to set the output voltage to levels as shown in Table 1. The RSET resistor is placed between the VSET pin and SGND.
TABLE 1. OUTPUT VOLTAGE RESISTOR SETTINGS VOUT (V) 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.50 2.80 3.00 3.30 4.00 RSET (k) 10 11 12.1 13.3 14.7 16.2 17.8 19.6 21.5 23.7 26.1 28.7 31.6 34.8 38.3 42.2 46.4 51.1 56.2 61.9 68.1 75 82.5 90.9 100 110 121 133 147 162
The output voltage may also be set to any value between 0.6V and 4.0V using a PMBus command over the I2C/SMBus interface. See Application Note AN2033 for details.
Soft-start Delay and Ramp Times
It may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. In addition, the designer may wish to precisely set the time required for VOUT to ramp to its target value after the delay period has expired. These features may be used as part of an overall inrush current management strategy or to precisely control how fast a load IC is turned on. The ZL9101M gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. The soft-start delay period begins when the EN pin is asserted and ends when the delay time expires. The soft-start delay and ramp times are set to custom values via the I2C/SMBus interface. When the delay time is set to 0ms, the device will begin its ramp-up after the internal circuitry has initialized (approximately 2ms). When the soft-start ramp period is set to 0ms, the output will ramp up as quickly as the output load capacitance and loop settings will allow. It is generally recommended to set the soft-start ramp to a value greater than 500s to prevent inadvertent fault conditions due to excessive inrush current.
Power Good
The ZL9101M provides a Power Good (PG) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. By default, the PG pin will assert if the output is within 10% of the target voltage. These limits and the polarity of the pin may be changed via the I2C/SMBus interface. See Application Note AN2033 for details. A PG delay period is defined as the time from when all conditions within the ZL9101M for asserting PG are met to when the PG pin is actually asserted. This feature is commonly used instead of using an external reset controller to control external digital logic. By default, the ZL9101M PG delay is set equal to the soft-start ramp time setting. Therefore, if the soft-start ramp time is set to 10ms, the PG delay will be set to 10ms. The PG delay may be set independently of the soft-start ramp using the I2C/SMBus as described in Application Note AN2033.
Switching Frequency and PLL
The ZL9101M incorporates an internal phase-locked loop (PLL) to clock the internal circuitry. The PLL can be driven by an external clock source connected to the SYNC pin. When using the internal oscillator, the SYNC pin can be configured as a clock source. The internal switching frequency of the ZL9101M is 615kHz.
Loop Compensation
The ZL9101M operates as a voltage-mode synchronous buck controller with a fixed frequency PWM scheme. The module is internally compensated via the I2C/SMBus interface. Please refer to Application Note AN2033 for further details.
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Adaptive Diode Emulation
Adaptive diode emulation mode turns off the low-side FET gate drive at low load currents to prevent the inductor current from going negative, reducing the energy losses and increasing overall efficiency. Diode emulation is available to single-phase devices only. Note: the overall bandwidth of the device may be reduced when in diode emulation mode. It is recommended that diode emulation is disabled prior to applying significant load steps. Please refer to Application Note AN2033 for details on how to select specific overvoltage fault response options via I2C/SMBus.
Output Pre-Bias Protection
An output pre-bias condition exists when an externally applied voltage is present on a power supply's output before the power supply's control IC is enabled. Certain applications require that the converter not be allowed to sink current during start up if a pre-bias condition exists at the output. The ZL9101M provides pre-bias protection by sampling the output voltage prior to initiating an output ramp. If a pre-bias voltage lower than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled. The output voltage is then ramped to the final regulation value at the preconfigured ramp rate. The actual time the output will take to ramp from the pre-bias voltage to the target voltage will vary depending on the pre-bias voltage but the total time elapsed from when the delay period expires and when the output reaches its target value will match the pre-configured ramp time. See Figure 10.
Input Undervoltage Lockout
The input undervoltage lockout (UVLO) prevents the ZL9101M from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. The UVLO threshold (VUVLO) can be set between 2.85V and 16V using the I2C/SMBus interface. Once an input undervoltage fault condition occurs, the device can respond in a number of ways as follows: 1. Continue operating without interruption. 2. Continue operating for a given delay period, followed by shutdown if the fault still exists. The device will remain in shutdown until instructed to restart. 3. Initiate an immediate shutdown until the fault has been cleared. The user can select a specific number of retry attempts. The default response from a UVLO fault is an immediate shutdown of the module. The controller will continuously check for the presence of the fault condition. If the fault condition is no longer present, the ZL9101M will be re-enabled. Please refer to Application Note AN2033 for details on how to configure the UVLO threshold or to select specific UVLO fault response options via the I2C/SMBus interface.
Output Overvoltage Protection
The ZL9101M offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. A hardware comparator is used to compare the actual output voltage (seen at the FB+ pin) to a threshold set to 15% higher than the target output voltage (the default setting). If the FB+ voltage exceeds this threshold, the PG pin will de-assert and the controller can then respond in a number of ways as follows: 1. Initiate an immediate shutdown until the fault has been cleared. The user can select a specific number of retry attempts. 2. Turn off the high-side MOSFET and turn on the low-side MOSFET. The low-side MOSFET remains ON until the device attempts a restart. The default response from an overvoltage fault is to immediately shut down. The controller will continuously check for the presence of the fault condition, and when the fault condition no longer exists the device will be re-enabled. For continuous overvoltage protection when operating from an external clock, the only allowed response is an immediate shutdown. 10
FIGURE 10. OUTPUT RESPONSES TO PRE-BIAS VOLTAGES
If a pre-bias voltage higher than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled with a PWM duty cycle that would ideally create the pre-bias voltage. Once the pre-configured soft-start ramp period has expired, the PG pin will be asserted (assuming the pre-bias voltage is not higher than the overvoltage limit). The PWM will then adjust its
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duty cycle to match the original target voltage and the output will ramp down to the preconfigured output voltage. If a pre-bias voltage higher than the overvoltage limit exists, the device will not initiate a turn-on sequence and will declare an overvoltage fault condition to exist. In this case, the device will respond based on the output overvoltage fault response method that has been selected. See "Output Overvoltage Protection" on page 10 for response options due to an overvoltage condition. Note that pre-bias protection is not offered for current sharing groups that also have tracking enabled. dropped below a threshold that is approximately +15 C lower than the selected temperature fault limit, the controller will attempt to re-start. If the temperature still exceeds the fault limit the controller will wait the preset delay period and retry again. The default response from a temperature fault is an immediate shutdown of the module. The controller will continuously check for the fault condition, and once the fault has cleared the ZL9101M will be re-enabled. Please refer to Application Note AN2033 for details on how to select specific temperature fault response options via I2C/SMBus.
Output Overcurrent Protection
The ZL9101M can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. The following overcurrent protection response options are available: 1. Initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. Continue operating for a given delay period, followed by shutdown if the fault still exists. 4. Continue operating through the fault (this could result in permanent damage to the power supply). 5. Initiate an immediate shutdown. The default response from an overcurrent fault is an immediate shutdown of the controller. The controller will continuously check for the presence of the fault condition, and if the fault condition no longer exists the device will be re-enabled. Please refer to Application Note AN2033 for details on how to select specific overcurrent fault response options via I2C/SMBus.
I2C/SMBus Communications
The ZL9101M provides an I2C/SMBus digital interface that enables the user to configure all aspects of the module operation as well as monitor the input and output parameters. The ZL9101M can be used with any I2C host device. In addition, the module is compatible with SMBus version 2.0. Pull-up resistors are required on the I2C/SMBus as specified in the SMBus 2.0 specification. The ZL9101M accepts most standard PMBus commands. When controlling the device with PMBus commands, it is recommended that the enable pin is tied to SGND.
I2C/SMBus Module Address Selection
Each module must have its own unique serial address to distinguish between other devices on the bus. The module address is set by connecting a resistor between the SA pin and SGND. Table 2 lists the available module addresses.
TABLE 2. SMBus ADDRESS RESISTOR SELECTION RSA0 10 11 12.1 13.3 14.7 16.2 17.8 19.6 21.5 23.7 26.1 28.7 31.6 34.8 38.3 42.2 46.4 51.1 56.2 SMBus Address 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B
Thermal Overload Protection
The ZL9101M includes a thermal sensor that continuously measures the internal temperature of the module and shuts down the controller when the temperature exceeds the preset limit. The default temperature limit is set to +125C in the factory, but the user may set the limit to a different value if desired. See Application Note AN2033 for details. Note that setting a higher thermal limit via the I2C/SMBus interface may result in permanent damage to the controller. Once the module has been disabled due to an internal temperature fault, the user may select one of several fault response options as follows: 1. Initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. Continue operating for a given delay period, followed by shutdown if the fault still exists. 4. Continue operating through the fault (this could result in permanent damage to the power supply). 5. Initiate an immediate shutdown. If the user has configured the module to restart, the controller will wait the preset delay period (if configured to do so) and will then check the module temperature. If the temperature has 11
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TABLE 2. SMBus ADDRESS RESISTOR SELECTION (Continued) RSA0 61.9 68.1 75 82.5 90.9 100 SMBus Address 0x2C 0x2D 0x2E 0x2F 0x30 0x31
powering advanced processors, FPGAs, and ASICs that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up from occurring. Multi-device sequencing can be achieved by configuring each device through the I2C/SMBus interface. Multiple device sequencing is configured by issuing PMBus commands to assign the preceding device in the sequencing chain as well as the device that will follow in the sequencing chain. The Enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. Enable must be driven low to initiate a sequenced turnoff of the group. Refer to Application Note AN2033 for details on sequencing via the I2C/SMBus interface.
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to communicate between Zilker Labs Digital-DC modules and devices. This dedicated bus provides the communication channel between devices for features such as sequencing, fault spreading, and current sharing. The DDC pin on all Digital-DC devices in an application should be connected together. A pull-up resistor is required on the DDC bus in order to guarantee the rise time as follows:
Fault Spreading
Digital DC modules and devices can be configured to broadcast a fault event over the DDC bus to the other devices in the group. When a nondestructive fault occurs and the device is configured to shut down on a fault, the device will shut down and broadcast the fault event over the DDC bus. The other devices on the DDC bus will shut down together if configured to do so, and will attempt to re-start in their prescribed order if configured to do so.
Rise Time = R PU C LOAD 1s
(EQ. 1)
where RPU is the DDC bus pull-up resistance and CLOAD is the bus loading. The pull-up resistor may be tied to an external 3.3V or 5V supply as long as this voltage is present prior to or during device power-up. As rules of thumb, each device connected to the DDC bus presents approximately 10pF of capacitive loading, and each inch of FR4 PCB trace introduces approximately 2pF. The ideal design will use a central pull-up resistor that is wellmatched to the total load capacitance. The minimum pull-up resistance should be limited to a value that enables any device to assert the bus to a voltage that will ensure a logic 0 (typically 0.8V at the device monitoring point) given the pull-up voltage and the pull-down current capability of the ZL9101M (nominally 4mA).
Active Current Sharing
Paralleling multiple ZL9101M modules can be used to increase the output current capability of a single power rail. By connecting the DDC pins of each module together and configuring the modules as a current sharing rail, the units will share the current equally within a few percent. Figure 11 illustrates a typical connection for two modules.
3.3V - 5V
VIN
CIN
Phase Spreading
When multiple point of load converters share a common DC input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. Setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. Since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the IRMS2 are reduced dramatically. In order to enable phase spreading, all converters must be synchronized to the same switching clock. The phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments via the I2C/SMBus interface. Refer to Application Note AN2033 for further details.
DDC
ZL
COUT
CIN
DDC
ZL
COUT
VOUT
FIGURE 11. CURRENT SHARING GROUP
Output Sequencing
A group of Digital-DC modules or devices may be configured to power up in a predetermined sequence. This feature is especially useful when
The ZL9101M uses a low-bandwidth, first-order digital current sharing technique to balance the unequal module output loading by aligning the load lines of member modules to a reference module. Droop resistance is used to add artificial resistance in the output voltage path to control the slope of the load line curve,
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calibrating out the physical parasitic mismatches due to power train components and PCB layout. Upon system start-up, the module with the lowest member position as selected in ISHARE_CONFIG is defined as the reference module. The remaining modules are members. The reference module broadcasts its current over the DDC bus. The members use the reference current information to trim their voltages (VMEMBER) to balance the current loading of each module in the system. operational. During periods of light loading, it may be beneficial to disable one or more phases in order to eliminate the current drain and switching losses associated with those phases, resulting in higher efficiency. The ZL9101M offers the ability to add and drop phases using a PMBus command in response to an observed load current change. All phases in a current share rail are considered active prior to the current sharing rail ramp to power-good. Any member of the current sharing rail can be dropped. If the reference module is dropped, the remaining active module with the lowest member position will become the new reference.
VREFERENCE -R VOUT VMEMBER -R
Additionally, any change to the number of members of a current sharing rail will precipitate autonomous phase distribution within the rail where all active phases realign their phase position based on their order within the number of active members. If the members of a current sharing rail are forced to shut down due to an observed fault, all members of the rail will attempt to re-start simultaneously after the fault has cleared.
Monitoring via I2C/SMBus
I MEMBER I OUT I REFERENCE
FIGURE 12. ACTIVE CURRENT SHARING
A system controller can monitor a wide variety of different ZL9101M system parameters through the I2C/SMBus interface. The module can monitor for any number of power conversion parameters including but not limited to the following: * Input voltage/Output voltage * Output current * Internal temperature * Switching frequency * Duty cycle Please refer to Application Note AN2033 for details on how to monitor specific parameters via the I2C/SMBus interface.
Figure 12 shows that, for load lines with identical slopes, the member voltage is increased towards the reference voltage which closes the gap between the inductor currents. The relation between reference and member current and voltage is given by the following equation:
VMEMBER = VOUT + R x (I REFERENCE - I MEMBER )
(EQ. 2)
where R is the value of the droop resistance. The ISHARE_CONFIG command is used to configure the module for active current sharing. The default setting is a stand-alone non-current sharing module. A current sharing rail can be part of a system sequencing group. For fault configuration, the current share rail is configured in a quasi-redundant mode. In this mode, when a member module fails, the remaining members will continue to operate and attempt to maintain regulation. Of the remaining modules, the module with the lowest member position will become the reference. If fault spreading is enabled, the current share rail failure is not broadcast until the entire current share rail fails. The phase offset of (multi-phase) current sharing modules is automatically set to a value between 0 and 337.5 in 22.5 increments as follows:
Snapshot Parameter Capture
The ZL9101M offers a special feature that enables the user to capture parametric data during normal operation or following a fault. The Snapshot functionality is enabled by setting bit 1 of MISC_CONFIG to 1. See AN2033 for details on using SnapShot in addition to the parameters supported. The Snapshot feature enables the user to read parameters via a block read transfer through the SMBus. This can be done during normal operation, although it should be noted that reading the 22 bytes will occupy the SMBus for some time. The SNAPSHOT_CONTROL command enables the user to store the snapshot parameters to Flash memory in response to a pending fault as well as to read the stored data from Flash memory after a fault has occurred. Table 3 describes the usage of this command. Automatic writes to Flash memory following a fault are triggered when any fault threshold level is exceeded, provided that the specific fault's response is to shut down (writing to Flash memory is not allowed if the device is configured to re-try following the specific fault condition). It should also be noted that the module's VDD voltage must be maintained during the time when the controller is writing the data to Flash memory;
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Phase Offset = SMBus Address [ 4:0 ] - Current Share Position 22.5
(EQ. 3)
Please refer to Application Note AN2034 for additional details on current sharing.
Phase Adding/Dropping
The ZL9101M allows multiple power converters to be connected in parallel to supply higher load currents than can be addressed using a single-phase design. In doing so, the power converter is optimized at a load current range that requires all phases to be 13
ZL9101M
a process that requires between 700s to 1400s depending on whether the data is set up for a block write. Undesirable results may be observed if the device's VDD supply drops below 3.0V during this process.
TABLE 3. SNAPSHOT_CONTROL COMMAND DATA VALUE 1 2 DESCRIPTION Copies current SNAPSHOT values from Flash memory to RAM for immediate access using SNAPSHOT command. Writes current SNAPSHOT values to Flash memory. Only available when device is disabled.
Non-Volatile Memory and Device Security Features
The ZL9101M has internal non-volatile memory where user configurations are stored. Integrated security measures ensure that the user can only restore the module to a level that has been made available to them. During the initialization process, the ZL9101M checks for stored values contained in its internal non-volatile memory. The ZL9101M offers two internal memory storage units that are accessible by the user as follows: 1. Default Store: The ZL9101M has a default configuration that is stored in the Default Store in the controller. The module can be restored to its default settings by issuing a RESTORE_DEFAULT_ALL command over the SMBus. 2. User Store: The user can modify certain power supply settings as described in this data sheet. The user would use the User Store to store their configuration. Please refer to Application Note AN2033 for details on how to set specific security measures via the I2C/SMBus interface.
In the event that the module experiences a fault and power is lost, the user can extract the last SNAPSHOT parameters stored during the fault by writing a 1 to SNAPSHOT_CONTROL (transfers data from Flash memory to RAM) and then issuing a SNAPSHOT command (reads data from RAM via SMBus).
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ZL9101M Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 1/20/2011 REVISION FN7669.1 CHANGE On page 5 Electrical Spec Table under Input and Supply Characteristic - Parameter "Input Supply Current, IVIN" conditions column changed from "VIN = 14V, IOUT = 15A, VOUT = 1.2V" to "VIN = 13.2V, IOUT = 15A, VOUT = 1.2V. Under Output Characteristics - Parameter "Line Regulation Accuracy" conditions column changed from "VOUT = 1.2V, IOUT = 0A, VIN = 5V to 14V" to "VOUT = 1.2V, IOUT = 0A, VIN = 5V to 13.2V". On page 1, under Features, changed "Tracking" to "Output Voltage Tracking" On page 1, Figure 1, added footnote 4. "The VR, V25, VDRV, and VDD capacitors should be placed no further than 0.5 cm from the pin." On page 5, under "Absolute Maximum Ratings", changed value: DC Supply Voltage for VDD Pin from 16V to 15.7V On page 5, under "Absolute Maximum Ratings", changed value: Input Voltage for VIN Pin from 16V to 15.7V On page 5, under Recommended Operating Conditions, changed value: Input Supply Voltage Range, Vin from 14V to 13.2V On page 5, under Recommended Operating Conditions, changed value: Input Supply For Controller, VDD from 14V to 13.2V On page 7, Note 11, changed "... for internal IC prior ..." to "... for internal controller prior ..." On page 8, Figure 7, changed title from "Ramp-up" to "Soft-start Ramp-up" On page 8, Figure 9A, changed labels to from V to VOUT (e.g. 3.3VOUT, 1.0VOUT) On page 8, Figure 9B, changed labels to from V to VOUT (e.g. 3.3VOUT, 1.0VOUT) FN7669.0 Initial release
1/11/2011
12/20/2010
Products
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For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com
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Package Outline Drawing
L21.15x15
21 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) Rev 0, 10/10
X4 A 17x 0.80 PIN 1 INDEX AREA 1 21 20 19 2 3 4 5 6 7 8 9 101112 13 14 15 15.00.2 15.80.2 18 2.95 17 17 3.1 6.3 7.25 18 19 20 21 1 2 3 4 5 6 7 8 9 9x 1.90.05 0.2 S AB
15.00.2
15.80.2
1.95
12.05
4.40
1.3 16 2.0 14 15
8.3
2.95
S 0.2
AAAAAAAA
AAAAAA
15
9 13 12 11 10
B
AAA
B CC
B
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17x 0.75 B
4.2 0.8
16
33x 0.5 0.05 S AB
ZL9101M
4.65 5.65
13
12 11 10
8x 1.80.05
TOP VIEW
BOTTOM VIEW
A
5 A LL
AAA
AROU ND
B
AAA
3.50.2
17
18
S
SIDE VIEW
0.50 S 0.05
16
14
19 20 21 1 2 3 4 5 6 7 8
B
A:1.3 0.1 B:2.6 0.1 C:1.13 0.1
7.0 6.2 5.7 4.9 4.4 3.6 3.1 2.3 0.7 0.0
0.1 0.6 4.2
6.9 8.3
6.0 5.6 4.8 4.3 3.5 3.0 2.2 1.7 0.9 0.4 0.0 0.4 0.9 1.7 2.2 3.0 4.8 5.6 6.0
8.3 6.9 5.6 5.0 4.2 1.1 0.3 0.0
1 21 2
4.1 4.9 5.6 8.3
6.1 5.5 4.9 4.2 3.6 2.9 2.3 1.6 1.0 0.3 0.0 0.3 1.0 1.6 2.3 2.9 4.9 5.5 6.1
6.9 6.3 5.6 5.0 4.3 3.7 3.0 2.4 0.6 0.0 0.0 0.9 1.5 2.2 2.8 3.5 4.1 6.8 8.2
1 21 2
8.2 6.8 5.5 5.1 4.0 3.6 2.9 2.3 1.6 1.2 0.1 0.0 0.3 1.0 1.6 2.3 2.9 3.6 4.0 5.1 5.5 6.8 8.2
8.3 6.1 5.5 4.7 4.2 3.4 3.0 2.2 0.7 0.0 0.1 0.6 1.4 2.2 4.8 5.6 6.9
8.3
6.2 5.4 4.8 4.1 3.5 2.9 2.3 0.6 0.0 0.7 1.3 2.3 2.8 3.5 4.1 6.1 6.7 8.2
0.0 0.9
3.4 4.0
6.5
STENCIL PATTERN WITH SQUARE PADS-2
0.0 0.7 2.4 2.5 3.0 4.2 4.5 4.8 5.8 6.3 6.5
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TYPICAL RECOMMENDED LAND PATTERN
STENCIL PATTERN WITH SQUARE PADS-1
1 21 2
6.4 5.3 3.9 1.4 0.8 0.0 0.05 1.6 2.2 3.8 5.1 6.4 NOTES: 1. 2. 3. Dimensions are in millimeters. Unless otherwise specified, tolerance : Decimal 0.2; Body Tolerance 0.2mm The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
0.0 1.2 1.8 3.8 4.4 5.8

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